In recent years, as electronic devices are becoming smaller and higher performing, there is a growing demand for providing inexpensive multilayer wiring boards that mount semiconductor chips such as LSIs at high density not only for industrial use but also for consumer use. Such multilayer wiring boards are required to electrically connect a plurality of fine pitch wiring patterns at high connection reliability.
To meet the market request, there have been proposed multilayer printed wiring boards having an interstitial via hole structure (hereinafter, IVH structure), which is easy to achieve high density wiring.
A multilayer printed wiring board having the IVH structure includes interlayer dielectric layers forming a laminated body, and via holes and through holes made of electroless plating and electroplating. The via holes electrically connect inner layer conductor circuit patterns or between inner layer conductor circuit patterns and outer layer conductor circuit patterns. The through holes connect outermost layer conductor patterns.
One of the prior arts related to the present invention is Patent Document 1 shown below.
In conventional multilayer printed wiring boards, however, the difference in the coefficient of thermal expansion between insulating material and intercalating metal causes an internal stress, which may lead to breakage of plated through holes or plated via holes especially in a substrate having a thickness of 1 mm or more. Interlayer connection is formed at a temperature of 20 to 60° C. by plating and reaches its fatigue limits due to high temperature environment or cold heat stress. It has been tried to reduce the difference in the coefficient of thermal expansion by filling the insulating resin with an inorganic filler. It is, however, difficult to make the coefficient of thermal expansion of the insulating resin lower than that of the interlayer connection material.
Patent Document 1: Japanese Patent Unexamined Publication No. 59-175796